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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 8.0V ≤ V PWR = V BAT ≤ 40V , -40 ° C ≤ T A ≤ 125 ° C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CHARGE PUMP
Charge Pump
High-Side Switch On-Resistance
Low-Side Switch On-Resistance
Regulation Threshold Difference (13)(15)
R DS(on)_HS
R DS(on)_LS
V THREG
–
–
250
6.0
5.0
500
10
9.4
900
?
?
mV
Charge Pump Output Voltage (14) , (15)
V CP
V
I OUT = 40mA, 6.0V < V BAT < 8.0V
I OUT = 40mA, V BAT > = 8.0V
8.5
12
9.5
–
–
–
GATE DRIVE
High-Side Driver On-Resistance (Sourcing)
R DS(on)_H_SRC
?
V PWR = V BAT = 16V, -40 ° C ≤ T A ≤ 25 ° C
V PWR = V BAT = 16V, 25 ° C < T A ≤ 125 ° C
High-Side Driver On-Resistance (Sinking)
V PWR = V BAT = 16V
R DS(on)_H_SINK
–
–
–
–
–
–
6.0
8.5
3.0
?
High-Side Current Injection Allowed Without Malfunction (15) , (16)
I HS_INJ
–
–
0.5
A
Low-Side Driver On-Resistance (Sourcing)
R DS(on)_L_SRC
?
V PWR = V BAT = 16V, -40 ° C ≤ T A ≤ 25 ° C
V PWR = V BAT = 16V, 25 ° C < T A ≤ 125 ° C
–
–
–
–
6.0
8.5
Low-Side Driver On-Resistance (Sinking)
R DS(on)_L_SINK
–
–
3.0
?
V PWR = V BAT = 16 V
Low-Side Current Injection Allowed Without Malfunction (15) , (16)
I LS_INJ
–
–
0.5
Α
Gate Source Voltage, V PWR = V BAT = 40V
V
High-Side, I GATE = 0
Low-Side, I GATE = 0
(17)
V GS_H
V GS_L
13
13
14.8
15.4
16.5
17
High-Side Gate Drive Output Leakage Current, Per
Output (18)
I HS_LEAK
–
–
18
μA
Notes
13. When VLS is this amount below the normal VLS linear regulation threshold, the pump is enabled.
14. With recommended external components (1.0μF, MUR 120 diode). The Charge Pump is designed to supply the gate currents of a
system with 100A FETs in a 12V application.
15. This parameter is a design characteristic, not production tested.
16. Current injection only occurs during output switch transitions. The IC is immune to specified injected currents for a duration of
approximately 1 μs after an output switch transition. 1 μs is sufficient for all intended applications of this IC.
17. If a slightly higher gate voltage is required, larger bootstrap capacitors are required. At high duty cycles, the bootstrap voltage may not
recover completely, leading to a higher output on-resistance. This effect can be minimized by using low ESR capacitors for the bootstrap
and the VLS capacitors.
18. A small internal charge pump will supply up to 30 μ A nominal to compensate for leakage on the high-side FET gate output and maintain
voltages after bootstrap events. It is not intended for external components to be connected to the High-Side FET gate, but small amounts
of additional leakage can be accommodated.
33927
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
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